| Tools for Quality Of service Validation, Development and Integration of critical computer Systems |
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document.write(' SPACEBEL’s QuoVadis section specialises on a coherent set of productivity tools that focus on improving quality, productivity and time-to-market for space projects, especially during the testing, integration, validation and qualification phases. Flexible user configurability and automated testing have been the main design drivers. Our flagship products are configurable computer simulators called Target Simulators for ERC32 and ADSP 21020. They are complemented by a number of loadable ASIC simulators (1553, 1355) and JTAG based Target Emulators. All tools are an excellent starting point to build economic validation facilities and operational simulators. \nWe offer maintenance contracts for GNU C compiler chains for ESA processors (Fresco). '); document.write('  QuoVadis_ds.pdf'); document.write(' |
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| ERC32 Target Simulator |
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document.write(' The Target Simulator is a tool that allows to simulate a computer that is built around the ERC32 32bit core (discrete and single chip versions). Besides the IU, FPU, MEC, it simulates input/output UART activity, watchdog, timers, interrupts (including errors) and DMA transfers with a resolution of one clock cycle. \nIts generic marker detection system, that can activate breaks, traces and traps for the OS emulation and I/O simulation subsystems, provides the tool more versatility than modern In-Circuit Emulators, while being completely non-intrusive. It provides a very good register visibility, a high accuracy and allows to single step interrupt routines and inject interrupts and errors. \nDebugging features have been added including the coverage feature and the trace history mechanism that buffers the local bus accesses by the CPU or other bus masters, such as the DMA. The coverage feature noting coverage of executed (tested) code, read before write detection and adding additional write protection. This is a valuable feature for qualifying critical systems (dead code and untested code detection). \nThe full hardware and software context can be saved and restored, which allows to bypass long preparation phases for complex test sequences. It is fully user re-configurable in terms of clock speeds and memory banks, sizes and access speeds. \nThe power of the tool stems from its flexibility. All its interfaces are Tcl based and can be redirected to communicate with scripts and external processes. \nIt can interface in a non-intrusive way via the command window with its integrated debugger, or with other debuggers and test systems, such as Aonix ADA cross compiler debugger, the GNU debugger and the SVF from ESA. \nNEW! The TS is running on Sun/Solaris 2.6 and above, and on PC/Linux. It is distributed as a stand alone product or as a library. '); document.write(' erc32_ts_ds_2003.pdf'); document.write(' |
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| ERC32 Target Emulator |
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document.write(' The ERC32 JTAG Target Emulator is basically the same product as the ERC32 Target Simulator. Its major difference is that the simulator is replaced by a serial JTAG connection into the on-chip debugger of any ERC32SC (Atmel TSC695) based multi-chip module and computer. \nThe ERC32 on-chip debugger functions completely independent from the processor. When there is something to be done, the whole ERC32 architecture, including it clocks, is frozen while we have complete control and visibility of all chip internals. The full hardware and software context can be saved and restored. Today, the Target Emulator is used in Europe, USA and China. '); document.write(' |
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| DSP 21020 Target Simulator |
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document.write(' Building further on its highly successful set of ERC32 tools, a 21020 version of the Target Simulator has been introduced. It simulates not only all internals of the Analog Device and Atmel 21020, it can be augmented with the DSP Peripheral Controller (DPC) chip. The simulated computer can be expanded with 1553 and 1355, along with associated medium simulators. \nThe DSP TS is distributed as a component of the DSP Fresco Toolset. '); document.write('  /en/space/frescodsp.htm '); document.write(' '); document.write(' DSP_TS_ds.pdf'); document.write(' |
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| Loadable ASIC & Medium Simulators |
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document.write(' Expanding the usability of its family of Target Simulators, Spacebel build a series of loadable ASIC simulators than can expand the simulated computer. Currently, we have ASIC simulators for 1355 and Mil-STD-1553. \nAlong with the ASIC simulators, we have the associated medium simulators that allow to connect several Target Simulators over the medium to simulate multi-computer systems. Please consult Spacebel concerning this fast growing family of simulators. '); document.write(' |
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| FRESCO GNU C Tools Maintenance for ERC32 |
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document.write(' FRESCO is a cooperation between ESA, Spacebel and Chris Nettleton Software to offer to the space industry a stable space qualified GNU tool chain for ERC32 processors. \nSpacebel offers commercial maintenance contracts for these tools. '); document.write(' http://www.estec.esa.nl/wmwww/EME/R ...'); document.write(' '); document.write(' |
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| Fresco C. Tools Maintenance for DSP21020 |
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document.write(' Fresco DSP is a co-operation between ESA and SPACEBEL to offer to the Space industry a stable development software toolset for the DSP21020. \nThe maintained tools include: compiler chain, libraries, simulator and emulator. '); document.write(' /en/space/frescodsp.htm '); document.write(' '); document.write(' |
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| ARBEOS |
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document.write(' ARBEOS is an innovating real-time object request broker targeting embedded distributed and parallel systems. \nIt allows to develop applications on any (SMP) PC or workstation configuration and deploy them on any distributed and parallel embedded configuration, including clusters of DSP’s. '); document.write(' Arbeos_ds.pdf'); document.write(' |
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| LEON |
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document.write(' The LEON Target Simulator developed by SPACEBEL for ESA is now available. It is an evolution of our ERC32 Target Simulator that simulates a LEON II processor based computer at instruction level. Like its predecessor, it is provided as a stand-alone tool (with facility to debug code at assembly level or to connect a debugger like GDB) and as a library, allowing integrating it in higher level simulation systems. '); document.write(' LEON_Datasheet.pdf'); document.write(' |
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